The present invention relates generally wafer level processing of integrated circuits. More particularly, a wafer level packaging arrangement is described that permits electrical testing and/or processing of both bump connectors and probe pads to be accomplished during a single probing sequence.
Electrical testing may be performed to identify non-operational chips on the wafer before the chips are diced and packaged. The electrical testing may be done through probe pins on the probe cards that contact the probe pads.
Probe pad types may be pads that are for customer use and pads that are solely for manufacturer use. The probe pads that are needed for customer applications will be connected to outer connection of the final package. Final electrical testing will be done on the outer connection before shipping the product to customer. The probe pads that are connected to the final package for the customer use are called “pin out pads”. The probe pads that are not connected to the final package but are instead solely for manufacturer use are called “internal pads”.
In conventional packaging, the connection of the pin out pad to the final package may be done by bonding the typically gold wire to a lead-frame. In the chip scale package, the connection may be created by placing the bump connectors, such as solder balls or other conductive bumps, on the pin out pad.
The current technology of electrical testing on wafer uses a probe card that has all the probe pin planarized in a single plane to make contact to the probe pads that are in a single plane. This is called a single level testing method.
The limitation of the current electrical testing technology does not allow probing on the “internal pads” and bumps simultaneously. This results in the use of two pass testing. A first pass testing is done on all the probe pads before the bumps are put on the chip. The first pass testing is also called pre-bump test. A second pass testing is done on the bump ball that is placed on the pin-out pads. The second pass testing is also called post-bump test. The primary purpose of the pre-bump test may be to identify an operational chips and/or further process the chips and the purpose of post-bump electrical testing on the packaged part may be to screen out defects in the bump packaging process.
In one example of further processing that may occur during the first pass processing, a variety of semiconductor devices (particularly precision analog semiconductor devices) requires that the circuits be trimmed after fabrication. Generally, trimming is the process of fine-tuning the performance of an integrated circuit device after fabrication in order to ensure conformance to a desired performance specification. In order to facilitate trimming, some of the internal pads are used as “trim pads” on the active surface of the die. Generally, a specific current is applied to each trim pad at a specific voltage in order to activate components (e.g. fuses) that can adjust the performance of the circuits of interest.
One example of using bump connectors is commonly referred to as “flip chip” packaging generally contemplates forming solder bumps (or other suitable contacts) directly on the face of an integrated circuit die. In some situations, the contacts are formed directly on I/O pads formed on the die, whereas in other situations the contacts are redistributed. The die is then typically attached to a substrate such as a printed circuit board or a package substrate such that the die contacts directly connect to corresponding contacts on the substrate.
When trim pads are included in flip chip package designs (or other wafer level chip scale packages) it is common to deposit a passivation material over the trim pads after the device has been trimmed. By way of example, a representative process might proceed as illustrated in FIG. 1. Specifically, after the wafer is fabricated (step 102), the wafer is taken to a wafer prober which tests and trims the appropriate circuits (step 104). The trim pads are generally formed from aluminum and thus they will corrode if left exposed in an ambient environment. Also, if they are left exposed when the singulated die is soldered to a substrate, there is a significant risk that the solder may bridge the gap between one of the bond pad/trim pad pairs, thereby shorting out the die. To avoid these problems, some manufacturing approaches contemplate covering the trim pads with a passivation material after the wafer has been trimmed. This helps reduce corrosion of the trim pads (step 106). Typically, the passivation layer also extends over edge portions of the I/O pads as well. Thus, the passivation layer is used to isolate the trim pads.
After the passivation layer is applied, appropriate underbump metallization stacks are typically formed on the I/O pads (step 108) and the wafer is bumped (step 110). It should be appreciated that there may be a number of other processing steps that occur before, as part of, or after the bumping. When the desired processing is completed, the wafer is again taken to a wafer prober where the final testing occurs.
In this scenario, wafer probe testing must be done twice. Initially, the wafer must be probed to facilitate trimming, which must occur before the trim pads are insulated by the passivation material. The wafer must also be probed a second time to test for electrical function after the contact bumps have been placed on the dies. Although the described process works well, this two-part wafer probing process is inefficient, since the wafer must go to a testing facility for trimming, and subsequently, to a manufacturing facility to cover the trim pads and then back to the testing facility for the final wafer probing before the dies are cut and shipped to customers. These inefficiencies add to the overall cost of manufacturing these IC devices. Therefore, there are continuing efforts to reduce the costs and time associated with the manufacturing process.
Other wafers that have internal pads and bump connectors may also require at least two separate wafer probings.